Non-Uniform Cache Apparatus (NUCA), System and Method
Description
Traditional cache hierarchies are broken up into levels (L1, L2, L3, etc.) where each successive level is much larger and slower than the previous one. If a needed datum is not found in the fastest level, L1, in one to three cycles, the slower L2 is searched, taking 6 to 12 cycles, and so on. The increase in wire delays makes these discrete levels infeasible for caches integrated with the processor on the same silicon die, as, even within one level, the number of cycles will vary depending upon where in that level the data reside.
Benefits
- Improves computer system performance over conventional cache of the same area
- Flexible across range of applications
- Scales and improves with technology advancements
- Performance improves as it scales with cache size
Features
- Mitigates the effect of slowing wires and provides high adaptivity
- Allows sophisticated allocation and sharing policies atop the basic NUCA structure
- Flattens memory hierarchy
- Stable organization
- Optimum cache size for each application
Market Potential/Applications
The market is any high performance microprocessor vendor, particularly Intel, IBM, Sun, HP, and AMD. The workloads that would show benefits from this invention being incorporated onto the processors include server workloads (such as web serving, transaction processing, or databases), high-end consumer programs (such as games), or scientific/technical workloads (such as number crunching or engineering with CAD tools).
For further information please contact
University of Texas,
Austin, USA
Website : www.otc.utexas.edu
