Method and Apparatus for Low-Power Branch Prediction

Introduction

Effective prediction remains a key enabler of high-end microprocessor performance, for branches, load/store dependencies, load cache hits, and other phenomenon. Modern branch predictors have gotten more and more complex, and now use considerable state and energy, and are also susceptible to soft errors, hard errors, and process variation, which are all growing in importance as the industry moves to smaller semiconductor devices.

Benefits

• Makes highly accurate neural-based predictors competitive from a power perspective for the first time
• Can be operated with very high power efficiency, accuracy and low latency
• Tolerant of soft errors, hard run-time faults, and process variation
• Highly resilient in the face of process variation and device errors

Market Potential/Applications

High-performance, low-power data processing systems

For further information please contact

University of Texas,
Austin, USA
Website : www.otc.utexas.edu