A Method and Apparatus for Scalable Bus-Based On-Chip Interconnection Networks

Introduction

Single-chip multiprocessors, or CMPs, have emerged as the leading alternative to complex monolithic uniprocessors. By placing multiple cores on a single die, complexity is managed via replication and design reuse, while power is kept in check through the use of less aggressive micro architectures. Today's most expansive designs have dozens of tiled cores on a chip, and with continued technology scaling, we can expect hundreds of general and special-purpose cores integrated on a single silicon substrate in the near future.

In order to interconnect such a high number of elements on a die, engineers have turned to interconnection networks as a replacement for conventional shared buses and ad hoc wiring solutions. On-chip interconnects are attractive due to their regularity and modular design, which can lead to better routability, electrical characteristics and fault tolerance. Most existing networks-on-a-chip (NOCs) are based on rings or two-dimensional meshes, topologies that have low design complexity and are a good fit to planar silicon substrates. These topologies, however, present serious scalability challenges as the core count increases into hundreds or thousands. In fact, two-dimensional (planar) semiconductor fabrication substrates restrict the space of implementable networks.

Benefits

• Provides better low-load latency than rings, meshes, and tori, because fewer hops are required
• Better low-load latency than other recently proposed network topologies, because each channel is wider, thus reducing the packet serialization latency
• More scalable, because channel count increases only linearly with the number of elements, allowing each channel to be wider

Market Potential/Applications

Computer interconnection networks, networks-on-chip, on-chip networks

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University of Texas,
Austin, USA
Website : www.otc.utexas.edu